In modern process technologies, transistor performance is highly dependent on the length of diffusion (LOD) past the transistor gate. This dependency may be caused by stress differences in the diffused region, depending on distance to shallow trench isolation (STI), and differences in localized heating between STI and diffused areas during flash annealing, to name just a couple of examples.
In many modern CMOS logic cell libraries, the diffusion is typically laid out in two rows: one row for P-type pMOSFETs (Metal Oxide Semiconductor Field Effect Transistor), and another row for nMOSFETs. Typical logic cell libraries break the diffusion at each cell's edge (border) in order to electrically isolate the transistors inside the cell from neighboring cells. Additionally, there are restrictions on the polysilicon (or metal-gate) layers that enforce a fixed patterning for the layer. These polysilicon patterning rules are such that typical logic cell layouts have a dummy polysilicon feature at a cell edge.
In other types of cell libraries, known as gate-array, a uniform diffusion and polysilicon pattern is used. In some forms of gate-array, the diffused area is not broken at the cell edge, but instead uses MOSFETs that are turned to electrically isolate logically non-equivalent nodes. One byproduct of these cell architectures is that the diffusion sizes (and thus MOSFET widths) are similar for all logic circuits that comprise the basic template of the gate array.